8 Cypress USB-Serial Windows Driver Installation Guide, Doc. 001- 87770 Rev *E Start Windows Update Search in Windows 7 Follow these steps to start the search in Windows 7 operating system: 1. Connect the USB-Serial device to the machine 2. Open Device Manager. To open Device Manager, click Start.
#boring_logicA 16-channel logic analyzer based on CY7C68013A MCU.
All hardware files are located in 'hardware' directry, including shematic, PCB, gerber files, and BOM.
R0A is an alpha version, and R01 is the final release.
In 'firmware' directry there are two EEPROM firmware files support Saleae Logic 8 and USBee AX Pro software. Firmwares are found from internet and only used for study.
To burn the firmware into EEPROM:
- Step1. Install driver in CypressToolsDriversCyLoad for CY7C68013A with blank EEPROM.
- Step2. Run CypressToolsbinCyConsole.exe and open options --> EZ-USB Interface.
- Step3. Select S EEPROM and choose the .iic file.
- (Note: Download a CySuiteUSB tool with newest version from Cypress website if the tools in firmware directory are no longer compatible with your OS)
When you want to reburn the EEPROM, just disconnect the jumper and redo from Step1 to Step3.
#For Windows7:Need to disable driver signature by pressing 'F8' key before loading the OS. Install CySuiteUSB and change the VID & PID numbers in INF driver file to match your device. Device VID & PID can be found in the windows device manager.
High-Speed USB Module
Features - USB 2.0 and 1.1 Compatible: High-Speed (480Mbps) and Full-Speed (12Mbps) - Integrated USB 2.0 transceiver, SIE, enhanced 8051 microcontroller, and a programmable peripheral interface - Four programmable bulk, interrupt or isochronous endpoints; Buffering options: double, triple or quad - Four integrated FIFOs, Master or slave operation; Easy interface to ASIC and DSP IC - Direct connection to most parallel 8/16 bits interfaces, data transfer rates up to 40MBytes per second - 24 general purpose I/Os - I2C master bus 100/400KHz - 16KB internal RAM for code and data - Software downloaded via USB or loaded from EEPROM - 24LC128 EEPROM - 5V and 3.3V max 0.3A outputs - Dimensions 60x35mm (2.4x1.4 inch) | Price & Order |
Application: The High-Speed USB Module is ideal for students or designer's that need to get up and running with High Speed USB immediately. It provides a solution for developers of new systems requiring USB 2.0 functionality or for adding on to existing systems that need USB 2.0 functionality. This module is based on the Cypress CY7C68013A microcontroller and can be used with Cypress EZ-USB FX2 Development Kit software and USB Developer's uStudio System Requirements: Windows 98/2000/XP, 128KB RAM, Pentium based PC at 700MHz and more Note: Cypress Generic USB Device Driver included in uStudio supports Windows 2000/XP only. EZ-USB FX2 Device Driver included in EZ-USB FX2 Development Kit supports Windows 98/2000/XP |
Software | |
FX2 Test v1.0 | available for High-Speed USB Module users only |
includes Windows 2000/XP driver, Keil uVision IDE, Cypress USB Console |
Projects based on the High-Speed USB Module or CY7C68013(A) |
J2 Connector Pin Descriptions | |||
Pin | Name | Type | Description |
1 | GND | Ground | |
2 | Vcc | Power | 3.3V max 0.3A |
3 | SDA | Open Drain | Data for I2C compatible interface ,2.2k pull-up resistor is connected to Vcc |
4 | SCL | Open Drain | Clock for I2C compatible interface ,2.2k pull-up resistor is connected to Vcc |
5 | IFCLK | I/O/Z | Interface Clock. use for synchronously clocking data into or out of the slave FIFOs |
6 | CTL0/FLAGA | Output | GPIF control Output; Programmable slave-FIFO output status flag signal |
7 | CTL1/FLAGB | Output | GPIF control Output; Programmable slave-FIFO output status flag signal |
8 | CTL2/FLAGC | Output | GPIF control Output; Programmable slave-FIFO output status flag signal |
9 | PA0/INT0 | I/O/Z | Bidirectional I/O port A pin; Active-low 8051 interrupt input signal |
10 | PA1/INT1 | I/O/Z | Bidirectional I/O port A pin; Active-low 8051 interrupt input signal |
11 | PA2/SLOE | I/O/Z | Bidirectional I/O port A pin; Output enable for the slave FIFO connected to FD[0-15] |
12 | PA3/WU2 | I/O/Z | Bidirectional I/O port A pin; USB wake up |
13 | PA4/FIFOADR0 | I/O/Z | Bidirectional I/O port A pin; Address select for the slave FIFO connected to FD[0-15] |
14 | PA5/FIFOADR1 | I/O/Z | Bidirectional I/O port A pin; Address select for the slave FIFO connected to FD[0-15] |
15 | PA6/PKTEND | I/O/Z | Bidirectional I/O port A pin; Packet end for the slave FIFO connected to FD[0-7/15] |
16 | PA7/FLAGD/SLCS | I/O/Z | Bidirectional I/O port A pin; Slave FIFO enable or output status flag signal |
17 | RESET | Input | Active low reset. Resets entire chip |
18 | WAKEUP | Input | USB wake up, starts oscillator, interrupts and exits the suspend mode |
19 | GND | Power | |
20 | PB0/FD0 | I/O/Z | Bidirectional I/O port B pin; Bidirectional FIFO/GPIF data bus |
21 | PB1/FD1 | I/O/Z | Bidirectional I/O port B pin; Bidirectional FIFO/GPIF data bus |
22 | PB2/FD2 | I/O/Z | Bidirectional I/O port B pin; Bidirectional FIFO/GPIF data bus |
23 | PB3/FD3 | I/O/Z | Bidirectional I/O port B pin; Bidirectional FIFO/GPIF data bus |
24 | PB4/FD4 | I/O/Z | Bidirectional I/O port B pin; Bidirectional FIFO/GPIF data bus |
25 | PB5/FD5 | I/O/Z | Bidirectional I/O port B pin; Bidirectional FIFO/GPIF data bus |
26 | PB6/FD6 | I/O/Z | Bidirectional I/O port B pin; Bidirectional FIFO/GPIF data bus |
27 | PB7/FD7 | I/O/Z | Bidirectional I/O port B pin; Bidirectional FIFO/GPIF data bus |
28 | PD0/FD8 | I/O/Z | Bidirectional I/O port D pin; Bidirectional FIFO/GPIF data bus |
29 | PD1/FD9 | I/O/Z | Bidirectional I/O port D pin; Bidirectional FIFO/GPIF data bus |
30 | PD2/FD10 | I/O/Z | Bidirectional I/O port D pin; Bidirectional FIFO/GPIF data bus |
31 | PD3/FD11 | I/O/Z | Bidirectional I/O port D pin; Bidirectional FIFO/GPIF data bus |
32 | PD4/FD12 | I/O/Z | Bidirectional I/O port D pin; Bidirectional FIFO/GPIF data bus |
33 | PD5/FD13 | I/O/Z | Bidirectional I/O port D pin; Bidirectional FIFO/GPIF data bus |
34 | PD6/FD14 | I/O/Z | Bidirectional I/O port D pin; Bidirectional FIFO/GPIF data bus |
35 | PD7/FD15 | I/O/Z | Bidirectional I/O port D pin; Bidirectional FIFO/GPIF data bus |
36 | CLKOUT | O/Z | 12-24-48 MHz clock, phase locked to the 24MHz input clock |
37 | RDY0/SLRD | Input | GPIF input signal; Read strobe for the slave FIFOs connected to FD[0-7/15] |
38 | RDY1/SLWR | Input | GPIF input signal; Write strobe for the slave FIFOs connected to FD[0-7/15] |
39 | GND | Ground | |
40 | USB5 | Power | 5V max 0.3A |